1. Field of the Invention
The present invention relates to a selector and a multilayer interconnection with a reduced occupied area on a substrate and particularly, to a plurality of selectors and a multilayer interconnection therefor in a semiconductor device.
2. Description of the Related Art
FIG. 17 shows a schematic configuration of a prior art multi-gradation liquid crystal display device of active matrix type. In FIG. 17, for simplicity, there is shown a case where a liquid crystal display panel 10 is of a monochrome display of 4xc3x974 pixels.
Data lines X1 to X4 of the liquid crystal display panel 10 simultaneously receives display potentials for one line from outputs of a data driver 20. Scanning pulses are line-sequentially provided to scanning lines Y1 to Y4 of the liquid crystal display panel 10 from outputs of a scanning driver 30. The data driver 20 updates the display potentials on the data line X1 to X4 at each scanning pulse. The data driver 20 and the scanning driver 30 are controlled by a control circuit 40, and the control circuit 40 generates various kinds of control signals on the basis of a horizontal sync signal HS, a vertical sync signal VS and a clock CK.
The data driver 20 comprises a shift register 21 for point-sequentially generating latch pulses LCH1 to LCH4, two stage buffer registers 221 to 224 and 231 to 234, and a digital-to-analog converter circuit that converts contents of registers 231 to 234 to analogue voltages. The digital-to-analog converter circuit comprises selectors 241 to 244, output buffer circuits 251 to 254, and a gradation-potential generation circuit 26.
The shift register 21 receives, at a serial data input, a start pulse SP1 having the same cycle time as that of the horizontal sync signal HS, and the serial input data is shifted by a clock CK1 that is a pixel clock CK having passed through a buffer gate, whereby the shift register 21 sequentially outputs the latch pulses LCH1 to LCH4 from the parallel output thereof.
A digital video signal D of parallel N bits is provided commonly to the registers 221 to 224 and held in the registers 221 to 224 in the timing of the latch pulses LCH1 to LCH4, respectively. After display data of one line are held in the registers 221 to 224, the contents of the registers 221 to 224 are respectively written in the registers 231 to 234 in the timing of a latch pulse LCH5 of the same cycle time as that of the horizontal sync signal HS and the contents of the registers 221 to 224 are retained there for a time interval of one horizontal cycle time (one cycle time of the horizontal sync signal HS). For the interval, data of a next display line are stored in the registers 221 to 224 in the same way as described above.
The scanning driver 30 comprises buffer gates 31 to 34, and a shift register 35, wherein inputs of the buffer gates 31 to 34 are connected to respective bit outputs of the shift register 35. Outputs of the buffer gates 31 to 34 are respectively connected to the scanning lines Y1 to Y4 of the liquid crystal display panel 10. The shift register 35 receives, at its serial data input, a start pulse SP2 having the same cycle time as that of a vertical sync signal VS, and the received serial data is shifted in the register 35 by a clock CK2 having the same cycle as that of the horizontal sync signal HS.
FIG. 18 shows an example of the above described digital-to-analog converter circuit. In FIG. 18, for simplicity, there is shown a case where an input is of 3 bits.
A gradation-potential generation circuit 26 outputs gradation potentials (reference potentials) V7 to V0 obtained with dividing a voltage between power supply potentials V7 and V0 by resistors R6 to R0. The selector 241 selectively outputs one of the gradation potentials V7 to V0 in response to an input data. Each bit of the input data consists of a pair of complementary signals, and generally a complementary signal of a bit D will be expressed by *D. The selector 241 is provided with analogue switch circuits each of which is constructed of switching transistors Qi0 to Qi2 serially connected to one another for each case of i=0 to 7. A gradation potential Vi is provided to one end of the analogue switch circuit having the transistors Qi0 to Qi2, and the other end thereof is commonly connected to an input end of the output buffer circuit 251. For each case of j=0 to 2, either of 1-bit selection signal Dj and *Dj is provided to the gate of a switching transistor Qij.
For example, when input data is xe2x80x98101xe2x80x99, switching transistors Q42, Q52, Q62, Q72, Q01, Q11, Q41, Q51, Q10, Q30, Q50 and Q70 are turned on and the other switching transistors are turned off. Thereby, only the analogue switch circuit constructed of the switching transistors Q52, Q51 and Q50 is turned on and the gradation potential V5 is selectively outputted to be provided to the output buffer circuit 251.
FIG. 19(A) shows a layout pattern of the selector 241, and portions shaded by hatching are N-type regions and portions drawn with dashed lines are gate lines. FIG. 19(B) is a sectional view taken on line 19Bxe2x80x9419B in FIG. 19(A), wherein insulator is not shown.
Referring back to FIG. 17, the liquid crystal display panel 10 is actually constituted of, for example, an array of 1024xc3x97768 color pixels each of which consists of 3 sub-pixels R (red), G (green) and B (blue). If the number of gradation levels of each pixel is 64 (6 bits), 64xc3x976 switching transistors are required for one selector. Therefore, a total number of switching transistors in all the selectors of the digital-to-analog converter circuit amounts to 1024xc3x973xc3x9764xc3x976=1,179,648, which is a cause for increase in chip area or area of a LCD panel peripheral portion. This problem also occurs in a semiconductor device using selectors of this kind for different applications.
Accordingly, it is an object of the present invention to provide a selector circuit that can reduce an area occupied by transistors on a substrate, and a semiconductor device, a digital-to-analog converter circuit and a liquid crystal display device each comprising the selector circuit.
It is another object to provide a semiconductor device and a display device in both of which wiring area can be reduced by multilayer interconnection, in a case where a plurality of the same circuits are arranged on a substrate substantially in a row, and lines, which provide a plurality of potentials to the circuits, are in parallel arranged in a congested manner above the circuits.
In the first aspect of the present invention, there is provided a selector circuit for selectively outputting one of 2n input signals in response to n-bit selection signals, comprising: 2nxe2x88x921 2-input selectors, each 2-input selector selecting one of two inputs in response to a 1-bit selection signal among the n-bit selection signals, and a 2nxe2x88x921 2-input selector for selecting one of signals selected by the 2nxe2x88x921 selectors in response to the n-bit selection signals except the 1-bit selection signal, wherein each of the 2nxe2x88x921 2-input selectors includes: a first switching transistor being on-off controlled by the 1-bit selection signal, the first switching transistor having an input for receiving one of the two inputs and having an output, and a second switching transistor being controlled so that its on/off state is reverse from that of the first switching transistor, the second switching transistor having an input for receiving the other of the two inputs and having an output connected to the output of the first switching transistor, wherein the first and second switching transistor of each 2-input selector are arranged in a row, and the 2nxe2x88x921 2-input selectors are arranged in parallel to one another.
With this aspect, since the number of signals is reduced in half by 2nxe2x88x921 2-input selectors, one of the signals whose number has been reduced in half is selected by a 2nxe2x88x921 input selector and therefore, the number of switching transistors of the selector circuit and a total area occupied by the switching transistors can be reduced. Further, because of the same row arrangement, it is possible to further reduce the total area occupied by transistors of the selector circuit.
In the second aspect of the present invention, there is provided a semiconductor device wherein a plurality of the same circuits are arranged substantially in a row, and lines for supplying potentials to the circuits are laid above the circuits, wherein the lines include a plurality of upper/lower trunk line pairs each consisting of an upper trunk line and a lower trunk line adjacent upper and lower, a plurality of line groups each consisting of two or three upper/lower trunk line pairs are arranged substantially in parallel to each other, and a distance between adjacent trunk lines in a connecting portion to a circuit, in the same wiring layer and of the same line group is substantially twice as long as a distance between adjacent line groups, wherein one of the upper trunk lines has a branched line toward an adjacent upper trunk line in the same wiring layer and of the same line group, the branched line is connected through an interlayer contact to a inter line which is in the lower wiring layer and parallel to the lower trunk lines.
With this aspect, more potential supply lines can be arranged in the same wiring area than when only second layer lines are arranged in parallel at the same pitch as in the prior art case, or when second and third layer lines are uniformly arranged at a pitch twice as large as a pitch in the prior art case. In other words, wiring area required in the prior art case can be reduced and thereby, a peripheral portion area of a display panel, on which a semiconductor chip or TFTs are provided, can be reduced.
Other aspects, objects, and the advantages of the present invention will become apparent from the following detailed description taken in connection with the accompanying drawings.